/*
 * Copyright 2024 ywcai
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *      http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */

`include "../core/defines.v"
`timescale 1ns/1ps

module rom(
	input   wire					clk,
	input   wire					rst_n,
	input   wire[`MemAddrBus]		pc_i,

	output  wire[`RegDataBus]		inst_o,
    output  wire[1:0]               errcode_o
	);

    reg[`InstDataBus]	_rom[0:`ROM_NUM - 1];
    reg[`InstDataBus]	test;

    reg[`MemAddrBus]	pc_offset;

    always @(posedge clk) begin
		if (rst_n == `RESET_ENABLE) begin
			pc_offset <= `ZERO_ADDR;
		end else begin
			pc_offset <= pc_i;
		end
    end

    assign inst_o = (rst_n == `RESET_ENABLE) ? `ZERO :
        {_rom[pc_offset[`ADDR_MSB:2]+1], _rom[pc_offset[`ADDR_MSB:2]]};
    assign errcode_o = 2'b00;

endmodule
